DocumentCode
1371640
Title
Four-quadrant analogue CMOS multiplier cell for VLSI signal and information processing
Author
Lau, K.T. ; Lee, S.T. ; Ong, V. K S
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Volume
145
Issue
2
fYear
1998
fDate
4/1/1998 12:00:00 AM
Firstpage
132
Lastpage
134
Abstract
A CMOS four-quadrant analogue multiplier cell for VLSI signal and information processing based on a transconductor and associated circuitry to cancel nonidealities is presented. It is designed to operate in the triode region. This multiplier is modular, has a large dynamic input range, high linearity, low power dissipation and can provide either a differential output current or voltage. The design was fabricated using a 1.2 μm CMOS process. Simulation and experimental results are presented and discussed
Keywords
CMOS analogue integrated circuits; VLSI; analogue multipliers; 1.2 micron; CMOS process; VLSI signal processing; differential output current; dynamic input range; four-quadrant analogue CMOS multiplier cell; linearity; nonidealities; power dissipation; transconductor; triode region;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings -
Publisher
iet
ISSN
1350-2409
Type
jour
DOI
10.1049/ip-cds:19981846
Filename
674082
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