A 600µA 32 kHz input 960 MHz output CP-PLL with 530ps integrated jitter in 28nm FD-SOI process

This paper presents a 32kHz input and 960MHz output low-power charge-pump phase-locked loop (CP-PLL) with a novel loop-filter resistor noise reduction technique and reverse sub-threshold leakage compensated source switched charge pump. The resistor noise reduction technique involves no additional active component / power overhead and hence, more beneficial than existing solutions. The PLL with minimum analog supply voltage of 1.62V and minimum digital supply voltage of 0.65V; with die area of 0.15mm² is designed and fabricated in 28nm STMicroelectronics FDSOI process. The silicon measurement results have been included. Performance includes an integrated jitter of 530ps, reference spur of -65dBc and current consumption of 600μA.