A 500MHz– 2.7 GHz 8-path weaver downconverter with harmonic rejection and embedded filtering

Author

Struiksma, Remko E. ; Klumperink, Eric A. M. ; Nauta, Bram ; van Vliet, Frank E.

Author_Institution

IC Design Group, Univ. of Twente, Enschede, Netherlands

fYear

2014

fDate

22-26 Sept. 2014

Firstpage

223

Lastpage

226

Abstract

This paper describes a combination of a Weaver mixer and an N-path filter for a superheterodyne receiver with a reconfigurable frequency plan. It uses an N-path topology driven with two different frequencies, effectively realizing a frequency shift together with band-pass filtering. To reduce transfers via harmonics other than the fundamental, a harmonic rejection scheme is used. A 28nm FDSOI CMOS implementation with 30 dB harmonic rejection and an out-of-band IIP3 of >20dBm is demonstrated.

Keywords

CMOS integrated circuits; UHF filters; UHF integrated circuits; UHF mixers; band-pass filters; elemental semiconductors; harmonics suppression; silicon; silicon-on-insulator; superheterodyne receivers; switched filters; 8-path weaver downconverter; FDSOI CMOS implementation; N-path filter topology; band-pass filtering; embedded filtering; frequency 500 MHz to 2.7 GHz; frequency shift; gain 30 dB; harmonic rejection scheme; out-of-band IIP3; reconfigurable frequency plan; size 28 nm; superheterodyne receiver; weaver mixer; Clocks; Frequency measurement; Frequency modulation; Harmonic analysis; Mixers; Radio frequency; N-path filter; Receiver; frequency conversion; harmonic rejection; image rejection; mixer; superheterodyne receiver;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th

Conference_Location

Venice Lido

ISSN

1930-8833

Print_ISBN

978-1-4799-5694-4

Type

conf

DOI

10.1109/ESSCIRC.2014.6942062

Filename

6942062