13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS

Author

Satpathy, Sudhir ; Mathew, Sanu ; Jiangtao Li ; Koeberl, Patrick ; Anders, Mark ; Kaul, Himanshu ; Chen, Gang ; Agarwal, Abhishek ; Hsu, Steven ; Krishnamurthy, Ram

Author_Institution

Intel Labs., Intel Corp., Hillsboro, OR, USA

fYear

2014

fDate

22-26 Sept. 2014

Firstpage

239

Lastpage

242

Abstract

A 250K probing-resilient PUF array with measured 2GHz operation and total energy consumption of 13fJ/bit at 0.9V, 25°C is fabricated in 22nm tri-gate CMOS. Hybrid PUF circuit with integrated load modulation and run-time soft dark-bit mask generation enables identification of unstable PUF bits with 100% accuracy, eliminating the need for multiple voltage/temperature characterization while also reducing bit-error down to 1.94%. Transient behavior of the hybrid PUF cell, along with the use of balanced local clock routing improves resiliency to invasive power-up probing attacks by 75%.

Keywords

CMOS integrated circuits; balanced local clock routing; bit-error; energy consumption; frequency 2 GHz; hybrid PUF circuit; integrated load modulation; invasive power-up probing attacks; multiple voltage-temperature characterization; physically unclonable functions; probing-resilient PUF array; run-time soft dark-bit mask generation; size 22 nm; temperature 25 degC; temperature 250 K; transient behavior; tri-gate CMOS; voltage 0.9 V; Arrays; CMOS integrated circuits; Clocks; Inverters; Latches; Logic gates; Modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th

Conference_Location

Venice Lido

ISSN

1930-8833

Print_ISBN

978-1-4799-5694-4

Type

conf

DOI

10.1109/ESSCIRC.2014.6942066

Filename

6942066