Title :
Performance Improvement of One-Transistor DRAM by Band Engineering
Author :
Pal, Ashish ; Nainani, Aneesh ; Gupta, Suyog ; Saraswat, Krishna C.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Abstract :
We propose a novel one-transistor (1T) quantum well (QW) DRAM with raised GaP source/drain. This novel device structure shows much better retention time and sense margin than the existing silicon 1T DRAM (with and without QW). Detailed simulation study indicates that the proposed structure is scalable up to 15-nm gate length. The proposed device utilizes nearly lattice-matched heterostructures which have already been realized in the literature.
Keywords :
DRAM chips; gallium compounds; quantum well devices; transistor circuits; IT QW DRAM; Si-GaP; band engineering; lattice-matched heterostructures; one-transistor quantum well DRAM; sense margin; silicon IT DRAM; size 15 nm; Charge carrier processes; Logic gates; Performance evaluation; Random access memory; Silicon; Silicon germanium; Tunneling; Gallium phosphide; heterostructure design; one-transistor (IT) DRAM; quantum well (QW);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2011.2171912
