Capacitance estimation for InAs Tunnel FETs by means of full-quantum k·p simulation

We report for the first time a quantum mechanical simulation study of gate capacitance components in aggressively scaled InAs Tunnel Field-Effect Transistor (TFET) nanowires. It will be shown that the gate-drain capacitance follows the same trend as the total gate capacitance (but with smaller values) over the whole V_gs range, hence confirming the capacitance estimation provided by semiclassical TCAD tools from a qualitative point of view. However, we find that the gate capacitance exhibits a nonmonotonic behavior as a function of the gate voltage, with plateaus and bumps, depending on the amount of energy quantization determined by the device cross-sectional size, and the position of channel-conduction subbands relative to the Fermi level in the drain contact. From this point of view, semiclassical TCAD tools seem to be inaccurate for capacitance estimation in aggressively scaled TFET devices.