Assessment of technological device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs

Author

Koyama, Masanori ; Casse, M. ; Barraud, S. ; Ghibaudo, Gerard ; Iwai, Hisato ; Reimbold, Gilles

Author_Institution

CEA LETI, Grenoble, France

fYear

2014

fDate

7-9 April 2014

Firstpage

57

Lastpage

60

Abstract

We report an experimental investigation of oxide/channel interface quality in SOI omega-gate nanowire NMOS FETs with cross-section as small as 10nm×10nm by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, H₂ anneal, or channel orientation. A method for rigorous contribution assessment of the two interfaces (top surface vs. side-walls) is also demonstrated. Excellent quality of the interfaces is extracted for all our technological and structural parameters.

Keywords

MOSFET; semiconductor device noise; silicon-on-insulator; H₂ annealing; SOI omega-gate nanowire NMOS FETs; channel orientation; low-frequency noise measurements; oxide-channel interface quality; strained channel; structural parameters; technological device parameter assessment; Annealing; Field effect transistors; Logic gates; Low-frequency noise; MOS devices; Silicon; Ω-gate nanowire transistors; SOI; low-frequency noise; oxide trap density; strained-SOI;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (ULIS), 2014 15th International Conference on

Conference_Location

Stockholm

Type

conf

DOI

10.1109/ULIS.2014.6813905

Filename

6813905