Title :
A transistor performance figure-of-merit including the effect of gate resistance and its application to scaling to sub-0.25-μm CMOS logic technologies
Author :
Chatterjee, Amitava ; Rodder, Mark ; Chen, Ih-Chin
Author_Institution :
Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA
fDate :
6/1/1998 12:00:00 AM
Abstract :
This paper presents an improved figure-of-merit (FOM) for CMOS performance which includes the effect of gate resistance. Performance degradation due to resistive polysilicon gates is modeled as an additional delay proportional to the RC product of a polysilicon line. The new FOM is verified from delay measurements on inverter chains fabricated using a 0.25-μm CMOS process. A furnace TiSi2 process is used to underscore the effect of increased sheet resistance of narrow polysilicon lines. Excellent correlation between measured and predicted inverter chain delays is obtained over a variety of design, process and bias conditions. An expression for the gate sheet resistance requirement is derived from the new FOM. Using this expression, requirements on the gate sheet resistance are calculated corresponding to a technology roadmap for performance and oxide thickness
Keywords :
CMOS logic circuits; MOSFET; electric resistance; integrated circuit design; integrated circuit technology; 0.25 micron; CMOS logic technologies; Si; TiSi2; bias conditions; delay measurements; furnace TiSi2 process; gate resistance; gate sheet resistance; inverter chains; narrow polysilicon lines; performance degradation; resistive polysilicon gates; submicron technology scaling; transistor performance figure-of-merit; Added delay; CMOS logic circuits; CMOS process; CMOS technology; Degradation; Delay effects; Electrical resistance measurement; Inverters; Semiconductor device modeling; Silicides;
Journal_Title :
Electron Devices, IEEE Transactions on
