Title :
Isomorph-redundancy in sequential circuits
Author :
Das, Debesh K. ; Bhattacharya, Uttam K. ; Bhattacharya, Bhargab B.
Author_Institution :
Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
fDate :
9/1/2000 12:00:00 AM
Abstract :
Design of irredundant and fully testable nonscan sequential circuits is a major concern of logic synthesis, as the presence of undetectable faults may render an ATPG intractable. This paper outlines some intriguing properties of isomorph faults, which are sequentially undetectable as well as redundant. An isomorph fault in a sequential circuit makes the state diagram of the faulty machine identical to that of the fault-free machine under certain renaming of states. Examples of reduced sequential machines whose circuit realization is combinationally irredundant, but isomorph-redundant, are hard to construct and very little is known about them. In this paper, many curious examples of such sequential circuits are presented wherein a single stuck-at fault causes isomorphic faulty machines. An infinite family of such circuits may, in fact, be constructed. It is shown that even two-level irredundant circuits obtained by synthesis tools may admit isomorph-redundancy under multiple stuck-at faults. Various classifications and related properties of isomorph faults are also reported. These results reveal new insight and understanding of redundancy in sequential circuits
Keywords :
automatic test pattern generation; logic design; logic testing; sequential circuits; ATPG; fault-free machine; fully testable nonscan sequential circuits; irredundant circuits; isomorph redundancy; logic synthesis; multiple stuck-at faults; renaming; stuck-at fault; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Electrical fault detection; Hardware; Logic testing; Redundancy; Sequential analysis; Sequential circuits;
Journal_Title :
Computers, IEEE Transactions on