Title :
Reduced thermal strain in flip chip assembly on organic substrate using low CTE anisotropic conductive film
Author :
Yim, Myung Jin ; Jeon, Young-Doo ; Paik, Kyung-Wook
Author_Institution :
Dept. of Mater. Sci. & Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fDate :
7/1/2000 12:00:00 AM
Abstract :
Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances, resulting in a high performance and cost-competitive packaging method. This paper describes the usefulness of low cost flip-chip assembly using electroless Ni/Au bump and anisotropic conductive films on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed as a low cost bumping method. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with Ni3P precipitation above 300°C causes an increase of hardness and an increase of the intrinsic stress. As interconnection material, modified ACFs composed of nickel conductive fillers for conductive fillers, and nonconductive fillers for modification of film properties, such as coefficient of thermal expansion (CTE), were formulated for improved electrical and mechanical properties of ACF interconnection. Three ACF materials with different CTE values were prepared and bonded between Si chips and FR-4 boards for the thermal strain measurement using moire interferometry. The thermal strain of the ACF interconnection layer, induced by temperature excursion of 80°C, was decreased according to the decreasing CTEs of ACF materials. This result indicates that the thermal fatigue life of ACF flip chip assembly on organic boards, limited by the thermal expansion mismatch between the chip and the board, could be increased by low CTE ACF
Keywords :
conducting polymers; filled polymers; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; light interferometry; moire fringes; thermal expansion; thermal stress cracking; CTE; FR-4; Ni-Au; anisotropic conductive film; conductive fillers; flip chip assembly; hardness; interconnection distances; intrinsic stress; low cost bumping method; moire interferometry; nonconductive fillers; organic substrate; package size; temperature excursion; thermal fatigue life; thermal strain; Assembly; Capacitive sensors; Conducting materials; Costs; Flip chip; Gold; Mechanical factors; Nickel; Packaging; Thermal expansion;
Journal_Title :
Electronics Packaging Manufacturing, IEEE Transactions on
DOI :
10.1109/6104.873244