Title :
Low-complexity, full-resolution, mirror- switching digital predistortion scheme for polar-modulated power amplifiers
Author :
Yu, W.-H. ; Cheng, W.-F. ; Li, Yuhua ; Cheang, C.-F. ; Mak, Pui-In ; Martins, Rui P.
Author_Institution :
State-Key Lab. of Analog & Mixed-Signal VLSI, Univ. of Macau, Macao, China
Abstract :
Proposed is a mirror-switching digital predistortion (DPD) scheme with low complexity and full resolution, tailored for power-efficient polar-modulated power amplifiers with nonlinear AM-AM and AM-PM characteristics. The involved digital circuitry is composed of just one CORDIC operator and two 1D look-up tables, avoiding any real-time interpolation or analogue operation. The DPD scheme is verified on a FPGA and the estimated power using a 65 nm CMOS technology is 5.2 mW. The training time is ~82 μs at a clock rate of 100 MHz. System-level simulations in MATLAB show significant improvements of error vector magnitude from 104.8 to 2 , and adjacent channel leakage ratio from 21.36 to 49.27 dB, under a 20 MHz-bandwidth 64-QAM OFDM test signal.
Keywords :
CMOS logic circuits; OFDM modulation; field programmable gate arrays; interpolation; power amplifiers; quadrature amplitude modulation; real-time systems; signal processing; table lookup; 1D look-up tables; 64-QAM OFDM test signal; AM-PM characteristics; CMOS technology; CORDIC operator; FPGA verification; MATLAB; adjacent channel leakage ratio; analogue operation; bandwidth 20 MHz; digital circuitry; error vector magnitude; frequency 100 MHz; low-complexity full-resolution mirror-switching digital predistortion scheme; mirror-switching DPD scheme; nonlinear AM-AM characteristics; polar-modulated power amplifiers; power 5.2 mW; power estimation; power-efficient polar-modulated power amplifiers; real-time interpolation; size 65 nm; system-level simulations;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2012.2073
