Title :
Vertical-Gate Si/SiGe Double-HBT-Based Capacitorless 1T DRAM Cell for Extended Retention Time at Low Latch Voltage
Author :
Shin, Ja Sun ; Choi, Hyunjun ; Bae, Hagyoul ; Jang, Jaeman ; Yun, Daeyoun ; Hong, Euiyoun ; Kim, Dae Hwan ; Kim, Dong Myong
Author_Institution :
Sch. of Electr. Eng., Kookmin Univ., Seoul, South Korea
Abstract :
A vertical-gate Si/SiGe double heterojunction bipolar transistor (VerDHBT)-based capacitorless 1T DRAM cell is proposed for improved storage performance with a fabrication feasibility through a selective epitaxy. It is verified through a TCAD device simulation for dc and transient characteristics of the proposed VerDHBT-based 1T DRAM. The off-state leakage current was significantly reduced, while the on-current was considerably increased with SIF/Bmid/DIF = SiGe/SiGe/Si as the interfacial source/middle body/interfacial drain. A large hysteresis window for the “read 1” from the “read 0” and a long retention time at low latch voltage could be also obtained.
Keywords :
DRAM chips; Ge-Si alloys; bipolar memory circuits; elemental semiconductors; heterojunction bipolar transistors; hysteresis; integrated circuit modelling; leakage currents; semiconductor device models; semiconductor epitaxial layers; silicon; technology CAD (electronics); transients; Si-SiGe-SiGe; TCAD device simulation; VerDHBT; dc characteristics; double heterojunction bipolar transistor; hysteresis; interfacial drain; interfacial source; latch voltage; off-state leakage current; on-current; retention time; selective epitaxy; transient characteristics; vertical gate Si-SiGe double HBT based capacitorless 1T DRAM cell; Hysteresis; Latches; Logic gates; Photonic band gap; Random access memory; Silicon; Silicon germanium; 1T DRAM; Capacitorless; DHBT; HBT; TCAD simulation; nonoverlap; retention time; vertical gate (VG);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2011.2174025
