A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells

Submicrometer static random access memory cells are more susceptible to particle strike soft errors and increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, analytical models for the critical charge variations accounting for both die-to-die and within-die variations are proposed. The derived models are verified and compared to Monte Carlo simulations by using industrial 65-nm CMOS technology. This paper provides new design insights such as the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability, especially, at lower supply voltages. It demonstrates that two extreme values of this coupling capacitor exist. The first value results in maximum relative variations and the other results in minimum relative variations. Therefore, the circuit designers can utilize these results to design the coupling capacitor to limit the variations under power and performance constraints in early design cycles. The derived analytical models account for the impact of the supply voltage and different particle strike conditions. These results are particularly important for soft error tolerant and variation tolerant designs in submicrometer technologies, especially, for low power operations.