Selection of Well Contact Densities for Latchup-Immune Minimal-Area ICs

Author

Dodds, N.A. ; Hutson, J.M. ; Pellish, J.A. ; Reed, R.A. ; Kim, H.S. ; Berg, M.D. ; Friendlich, M.R. ; Phan, A.M. ; Seidleck, C.M. ; Xapsos, M.A. ; Deng, X. ; Baumann, R.C. ; Schrimpf, R.D. ; King, M.P. ; Massengill, L.W. ; Weller, R.A.

Author_Institution

Vanderbilt Univ., Nashville, TN, USA

Volume

57

Issue

6

fYear

2010

Firstpage

3575

Lastpage

3581

Abstract

Heavy ion data for custom SRAMs fabricated in a 45-nm CMOS technology demonstrate the effects of N- and P-well contact densities on single-event latchup. Although scaling has improved latchup robustness, process-level immunity has not been achieved, indicating a continued need for latchup mitigation techniques. A simple, algorithmic approach for selecting N- and P-well contact densities is described that ensures latchup immunity while minimizing the area penalty.

Keywords

CMOS integrated circuits; SRAM chips; integrated circuit design; CMOS technology; N-well contact density; P-well contact density; custom SRAM; heavy ion data; latchup mitigation techniques; latchup robustness; latchup-immune minimal-area IC; process-level immunity; single-event latchup; well contact densities; CMOS technology; Radiation hardening; Resistors; SRAM chips; Design rule; external resistor; hardening by design; latchup test structure; single-event latchup;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2010.2082562

Filename

5658046