Title :
High-performance 0.1 μm-self-aligned-gate GaAs MESFET technology
Author :
Nishimura, Kazumi ; Onodera, Kiyomitsu ; Aoyama, Shinji ; Tokumitsu, Masami ; Yamasaki, Kimiyoshi
Author_Institution :
NTT Syst. Electron. Labs., Kanagawa, Japan
fDate :
11/1/1997 12:00:00 AM
Abstract :
We report on 0.1-μm gate-length self-aligned Au/WSiN-gate GaAs MESFET technology. The FET we produced using this technology has a planar structure with a selective ion-implanted channel layer and self-aligned n+- layers. One of the key structural parameters affecting device performance is the offset separating the gate electrode from lightly-doped source and drain n´ layers. A 0.1-μm gate length is attained by i-line photolithography using an anti-reflection top coat film and SF6 gas ECR plasma etching. We demonstrate FET uniformity in a 3-in wafer and excellent high-frequency performance. The standard deviation of the threshold voltages is 0.058 V with an average of about 0 V at a gate length of 0.126 μm and the current gain cutoff frequency (fT) is 168 GHz at a gate length of 0.06 μm
Keywords :
III-V semiconductors; Schottky gate field effect transistors; gallium arsenide; ion implantation; millimetre wave field effect transistors; photolithography; semiconductor device metallisation; sputter etching; 0.06 to 0.126 mum; 168 GHz; 3 inch; Au-WSiN-GaAs; FET uniformity; GaAs; GaAs MESFET technology; SF6; SF6 gas ECR plasma etching; anti-reflection top coat film; current gain cutoff frequency; drain n´ layers; gate electrode; gate length; high-frequency performance; i-line photolithography; lightly-doped source layers; offset; planar structure; selective ion-implanted channel layer; self-aligned Au/WSiN-gate; self-aligned n+- layers; structural parameters; threshold voltage standard deviation; ultra-high-speed ICs; Electrodes; FETs; Gallium arsenide; Gold; Lithography; MESFETs; Plasma applications; Plasma devices; Plasma sources; Structural engineering;
Journal_Title :
Electron Devices, IEEE Transactions on
