Title :
A four-level storage 4-Gb DRAM
Author :
Okuda, Takashi ; Murotani, Tatsunori
Author_Institution :
ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan
fDate :
11/1/1997 12:00:00 AM
Abstract :
A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each corresponding to two-bit-data storage in a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier using charge coupling and charge sharing was developed for the four-level sensing and restoring. The sense amplifier uses a hierarchical bit-line scheme and operates in a time-sharing mode, thus reducing the sense amplifier area. A 4-Gb DRAM fabricated using 0.15-μm CMOS technology measures 986 mm2. The memory cell is 0.23 μm2. Its capacitance of 60 fF is achieved by using a high-dielectric-constant material BST
Keywords :
CMOS memory circuits; DRAM chips; capacitance; memory architecture; 0.15 micron; 4 Gbit; 60 fF; BST; CMOS technology; DRAM; capacitance; charge coupling; charge sharing; four-level storage; hierarchical bit-line scheme; high-dielectric-constant material; large memory capacity; multilevel-storage memory cells; sense amplifier; time-sharing mode; Binary search trees; CMOS technology; Capacitance; Capacitors; Circuits; National electric code; Random access memory; Terrorism; Time sharing computer systems; Ultra large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
