Low Group Delay 3.1–10.6 GHz CMOS Power Amplifier for UWB Applications

This letter proposes the design of a low group delay ultra-wideband (UWB) power amplifier (PA) in CMOS technology. The PA design employs a three-stage cascade common source topology that has a different design concept from other multi-stage topology to provide a broad bandwidth characteristic, gain flatness of , and low group delay variation of . A resistive shunt feedback technique is adopted at the first stage of the amplifier to achieve good input matching, which controls the upper frequency of the UWB system. The third stage realizes the gain at the lower corner frequency and the second stage is used to smooth the flatness of the gain curve. By using this method, the proposed design has the lowest group delay variation among the recently reported CMOS PAs for 3.1 to 10.6 GHz applications.