Title :
Pipelined DFE architectures using delayed coefficient adaptation
Author :
Perry, R. ; Bull, David R. ; Nix, A.
Author_Institution :
Centre for Commun. Res., Bristol Univ., UK
fDate :
7/1/1998 12:00:00 AM
Abstract :
In this paper the delayed least-mean-square (DLMS) algorithm is proposed for training a transversal filter-based decision feedback equalizer (DFE). Delays in the filter coefficient update process are used to pipeline the DFE, thereby increasing the throughput rate, for a given speed of hardware. The filter structures selected for the feedforward and feedback section of the DFE facilitate the use of a shared error signal, thereby reducing communication costs. The new resulting structure is highly modular and is very suitable for very large scale integration (VLSI) implementation. A pipelined form for the normalized least-mean-square algorithm (NMLS) is also obtained which removes the dependency of the convergence speed on the input signal power. The convergence and residual mean-square error characteristics of the different pipelined filters are compared
Keywords :
VLSI; adaptive equalisers; adaptive filters; circuit feedback; convergence; data communication equipment; decision feedback equalisers; delays; digital filters; digital signal processing chips; feedforward; least mean squares methods; pipeline processing; VLSI implementation; convergence speed; decision feedback equalizer training; delayed LMS algorithm; delayed coefficient adaptation; delayed least-mean-square algorithm; feedback section; feedforward section; filter coefficient update process delays; modular structure; normalized LMS algorithm; normalized least-mean-square algorithm; pipelined DFE architectures; pipelined filters; residual mean-square error characteristics; shared error signal; throughput rate improvement; transversal filter-based DFE; Adaptive equalizers; Adaptive filters; Convergence; Decision feedback equalizers; Delay; Error correction; Least squares approximation; Signal processing algorithms; Transversal filters; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on