Title :
Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects
Author :
Mensink, Eisse ; Schinkel, Daniël ; Klumperink, Eric A M ; Van Tuijl, Ed ; Nauta, Bram
Author_Institution :
Bruco B.V., Borne, Netherlands
Abstract :
This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.
Keywords :
CMOS integrated circuits; RC circuits; capacitance; crosstalk; electric impedance; equalisers; integrated circuit interconnections; low-power electronics; network-on-chip; transfer functions; CMOS test chip; analog feedback; capacitive driver; capacitively driven RC-limited on-chip interconnects; cross-talk; data integrity; dynamic power consumption; flat transfer function; high data rate point-to-point communication; line termination impedance; linear phase; low offset dynamic sense amplifier; low-power decision feedback equalization; network on chip; on-chip RC-limited wire-pairs; parallel differential interconnects; point-to-point link; power efficient gigabit communication; receiver; resistive load; s-parameter wire-pair model; series capacitance; size 90 nm; Capacitance; Delay lines; Driver circuits; Energy consumption; Frequency; Impedance; Integrated circuit interconnections; Scattering parameters; Transfer functions; Voltage; CMOS; Capacitive coupling; NoC; RC-limited interconnects; communication techniques; de-emphasis; decision feedback equalization; equalization; low power electronics; low-swing; networks on chip; on-chip interconnects; on-chip wires; pre-emphasis;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2036761