Title :
Low-power area-efficient high-speed I/O circuit techniques
Author :
Lee, Ming-Ju Edward ; Dally, William J. ; Chiang, Patrick
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
Abstract :
We present a 4-Gb/s I/O circuit that fits in 0.1-mm/sup 2/ of die area, dissipates 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-/spl mu/m CMOS technology. Swing reduction is used in an input-multiplexed transmitter to provide most of the speed advantage of an output-multiplexed architecture with significantly lower power and area. A delay-locked loop (DLL) using a supply-regulated inverter delay line gives very low jitter at a fraction of the power of a source-coupled delay line-based DLL. Receiver capacitive offset trimming decreases the minimum resolvable swing to 8 mV, greatly reducing the transmission energy without affecting the performance of the receive amplifier. These circuit techniques enable a high level of I/O integration to relieve the pin bandwidth bottleneck of modern VLSI chips.
Keywords :
CMOS digital integrated circuits; delay lock loops; equalisers; high-speed integrated circuits; integrated circuit design; low-power electronics; timing jitter; 0.25 mum; 4 Gbit/s; 90 mW; CMOS technology; I/O integration; PCB trace; delay-locked loop; equalization; input-multiplexed transmitter; low jitter; low-power area-efficient high-speed I/O circuit techniques; minimum resolvable swing; offset cancellation; pin bandwidth bottleneck; power dissipation; receiver capacitive offset trimming; serial links; speed advantage; supply-regulated inverter delay line; swing reduction; transmission energy; Bandwidth; CMOS technology; Circuit noise; Delay lines; Integrated circuit interconnections; Inverters; Noise reduction; Power cables; Transmitters; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
