Title :
A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme
Author :
Atsumi, Shigeru ; Umezawa, Akira ; Tanzawa, Tooru ; Taura, Tadayuki ; Shiga, Hitoshi ; Takano, Yoshinori ; Miyaba, Takeshi ; Matsui, Michiharu ; Watanabe, Hiroshi ; Isobe, Kazuaki ; Kitamura, Shota ; Yamada, Seiji ; Saito, Masanobu ; Mori, Seiichi ; Watan
Author_Institution :
Memory LSI Res. & Dev. Centre, Toshiba Semicond. Co., Yokohama, Japan
Abstract :
A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-/spl mu/m triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 /spl mu/m/sup 2/, the smallest yet reported for 0.25-/spl mu/m CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized.
Keywords :
CMOS memory circuits; flash memories; high-speed integrated circuits; low-power electronics; 0.25 mum; 1.8 V; 32 Mbit; 90 ns; NOR flash EEPROM; access time; bitline direct sensing scheme; block decoder circuit; cell size; channel-erasing scheme; erase-reset sequence; high-speed reading operation; low voltage; triple-well double-metal CMOS process; wordline boosted voltage pooling method; CMOS technology; Circuits; Decoding; EPROM; Energy consumption; Flash memory; Large scale integration; Substrates; Tunneling; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
