The impact of scaling down to deep submicron on CMOS RF circuits

Author

Huang, Qiuting ; Piazza, Francesco ; Orsatti, Paolo ; Ohguro, Tatsuya

Author_Institution

Integrated Syst. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland

Volume

33

Issue

7

fYear

1998

fDate

7/1/1998 12:00:00 AM

Firstpage

1023

Lastpage

1036

Abstract

Recent papers reporting CMOS RF building blocks have aroused great expectations for RF receivers using deep-submicron technologies. This paper examines the trend in CMOS scaling, in order to establish the required current levels and achievable performance for different feature sizes, if robust, easily manufacturable designs are to be implemented for cellular applications. The boundary conditions (system-level constraints) for such designs, in terms of the number of trimmed and untrimmed external components and the roles they play in relaxing active circuit requirements, are emphasized throughout to make comparison of active RF circuits meaningful. At 1 GHz, 0.25-μm CMOS appears to be the threshold for robust, low-NF RF front ends with current consumption competitive with today´s BJT implementations

Keywords

CMOS integrated circuits; cellular radio; integrated circuit design; radio receivers; 0.25 micron; 1 GHz; CMOS RF circuit; RF front end; RF receiver; active circuit; cellular communication; current consumption; deep submicron technology; low-noise amplifier; low-power design; manufacture; scaling; Active circuits; Boundary conditions; CMOS technology; Low-noise amplifiers; Paper technology; Parasitic capacitance; Pulp manufacturing; Radio frequency; Robustness; Transconductance;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.701249

Filename

701249