A new low-power GaAs two-single-port memory cell

Author

Bernal, Alvaro ; Guyot, Alain

Author_Institution

TIMA Lab., Grenoble, France

Volume

33

Issue

7

fYear

1998

fDate

7/1/1998 12:00:00 AM

Firstpage

1103

Lastpage

1110

Abstract

This paper describes an experimental static memory cell in GaAs MESFET technology. The memory cell has been implemented using a mix of several techniques already published in order to overcome some of their principal drawbacks related to ground shifting, destructive readout, and leakage current effects. The cell size is 36×37 μm² using a 0.6-μm technology. An experimental 32 word × 32 bit array has been designed. From simulation results, an address access time of 1 ns has been obtained. A small 8 word×4 bit protoype was fabricated. The cell can be operated at the single supply voltage from 1 up to 2 V. The evaluation is provided according to the functionality and power dissipation. Measured results show a total current consumption of 14 μA/cell when operated at 1 V

Keywords

III-V semiconductors; MESFET integrated circuits; SRAM chips; cellular arrays; gallium arsenide; leakage currents; memory architecture; 0.6 micron; 1 ns; 1 to 2 V; 32 bit; III-V semiconductors; MESFET technology; address access time; cell size; destructive readout; functionality; ground shifting; leakage current effects; power dissipation; static memory cell; supply voltage; total current consumption; two-single-port memory cell; Driver circuits; FETs; Gallium arsenide; Laboratories; Leakage current; MESFETs; Microprocessors; Random access memory; Schottky diodes; Temperature;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.701272

Filename

701272