Title :
Partial-matching lossless data compression hardware
Author_Institution :
Dept. of Electron. & Electr. Eng., Loughborough Univ., UK
fDate :
10/1/2000 12:00:00 AM
Abstract :
A novel architecture is presented for a high-performance lossless data compressor. Organised around a selectively shiftable content-addressable memory, which permits partial (inexact) matching, the processor offers very high performance with modest technology and good compression of computer-based data. Details of the operation, architecture and performance are given.
Keywords :
data compression; Euclidean distance transformation; VLSI architecture; VLSI implementation; content-addressable memory; data compression; image analysis; parallel algorithm; partial-matching;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
DOI :
10.1049/ip-cdt:20000637
