Title :
Short-circuit energy dissipation modeling for submicrometer CMOS gates
Author :
Bisdounis, L. ; Koufopavlou, O.
Author_Institution :
Dept. of Electr. & Comput. Eng., Patras Univ., Greece
fDate :
9/1/2000 12:00:00 AM
Abstract :
A significant part of the energy dissipation in static complementary metal-oxide-semiconductor (CMOS) structures is due to short-circuit currents. In this paper, an accurate analytical model for the CMOS short-circuit energy dissipation is presented. First, the short-circuit energy dissipation of the CMOS inverter is modeled. The derived model is based on analytical expressions of the inverter output waveform which include the influences of both transistor currents and the gate-to-drain coupling capacitance. Also, the effect of the short-circuiting transistor´s gate-source capacitance on the short-circuit energy dissipation, is taken into account. The α-power law MOS model that considers the carriers´ velocity saturation effect of submicrometer devices is used. Second, the inverter model is extended to static CMOS gates by using reduction techniques of series- and parallel-connected transistors. The results produced by the suggested model for a commercial 0.8-μm process, show very good agreement with SPICE simulations.
Keywords :
CMOS logic circuits; SPICE; capacitance; circuit simulation; integrated circuit modelling; logic gates; logic simulation; α-power law MOS model; 0.8 micron; CMOS inverter; SPICE simulations; energy dissipation; gate-source capacitance; gate-to-drain coupling capacitance; parallel-connected transistors; reduction techniques; series-connected transistors; short-circuit energy dissipation modeling; submicrometer CMOS gates; transistor currents; velocity saturation effect; Analytical models; Capacitance; Circuit simulation; Energy dissipation; Inverters; MOSFETs; Power dissipation; SPICE; Semiconductor device modeling; Very large scale integration;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on