ITF-BSCC technology for 16 Mbit DRAM cell

A buried stacked capacitor cell (BSCC), one of the most suitable cell structures for 16-Mb DRAMs (dynamic random-access memories), suffers from two kinds of unfavorable current leakage paths: between the storage node and the substrate, caused by the gate controlled diode structure along the trench sidewall SiO₂; and between the neighboring cell contacts, caused by the punchthrough under the field SiO₂. To improve these problems, a BSCC with ion implantation through the field SiO₂ (ITF-BSCC) is reported. The key feature is a p⁺ region that is formed 0.4-0.6 μm from the Si substrate surface under the active region and isolation region. This p⁺ region acts as isolation under the field SiO₂ and as a potential barrier for the leakage current of the gate-controlled diode. This p⁺ region can be fabricated by boron ion implantation at 180-200 keV to a total dose of 5E11-1E12 cm ^-2. All steps of the processing except this boron ion implantation are the same as those of conventional BSCC. This leakage current of the gate-controlled diode with trenches fabricated by ITF-BSCC process and conventional BSCC process were measured. The peak leakage current of ITF-BSCC is 3-5 times lower than that of conventional BSCC