DocumentCode :
1407860
Title :
A novel germanium implanted salicide technology for CMOS VLSI
Author :
Pfiester, J.R.
Author_Institution :
Motorola Inc., Austin, TX
Volume :
35
Issue :
12
fYear :
1988
fDate :
12/1/1988 12:00:00 AM
Firstpage :
2436
Lastpage :
2437
Abstract :
A novel salicided twin-tub CMOS process using germanium implantation has been developed and characterized. Implantation of n+ and p+ dopants after titanium salicidation is used to fabricate devices with low junction leakage and good short-channel effects. The technology is based on a conventional twin-tub CMOS process that uses LTO sidewall spacers for both the LDD (lightly doped drain) and salicide formation. The high-dose phosphorus and boron implants that are performed through the silicide layer to form the n+ and p+ regions result in an enhanced diffusivity in the n- and p- regions, causing anomalously deep source-drain junctions with degraded device punchthrough leakage. This is confirmed by electrical measurements. Since the projected implantation range for phosphorus is greater than arsenic, thicker titanium silicide layers with lower sheet resistance are possible. Spreading resistance and electrical device measurements indicate that the lateral diffusion of the n- and p- regions is reduced by as much as 0.15 μm when germanium implantation is performed prior to titanium deposition. Diode leakage was less than 10 nA/cm2 for a 5 V bias at room temperature for both cases
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; ion implantation; CMOS VLSI; LDD; LTO sidewall spacers; Si:Ge; Si:P; SiB; TiSi2; deep source-drain junctions; degraded device punchthrough leakage; diode leakage; enhanced diffusivity; ion implantation; lateral diffusion; low junction leakage; n+ dopants; p+ dopants; salicided twin-tub CMOS process; sheet resistance; short-channel effects; spreading resistance; CMOS process; CMOS technology; Electric resistance; Electric variables measurement; Electrical resistance measurement; Germanium; Silicides; Space technology; Titanium; Very large scale integration;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.8850
Filename :
8850
Link To Document :
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