DocumentCode :
1408317
Title :
A novel, shallow-trench-isolated, planar, N+SAG FAMOS transistor for high-density nonvolatile memories
Author :
Esquivel ; Huffman, C. ; Paterson, J.L. ; Riemenschneider, B.R.
Author_Institution :
Texas Instrum. Inc., Dallas, TX
Volume :
35
Issue :
12
fYear :
1988
fDate :
12/1/1988 12:00:00 AM
Firstpage :
2437
Abstract :
The authors report the fabrication, for the first time, of a shallow-trench isolated (less than 1 μm deep) planarized, floating-gate avalanche injection MOS (FAMOS) transistor with n+ bitlines self-aligned to gate (n+ SAG). Key to the planar process is the self-alignment of the buried n+ diffusions (bitlines) to the floating gate of the FAMOS transistor and the deposition over these diffusions of a low-temperature, conformal CVD (chemical vapor deposition) oxide. An oxide-resist etchback process was used to planarize the buried n+ CVD oxide. Trench etching was done immediately after definition of the stacked polysilicon gates. Using an anisotropic etch for single-crystal silicon, trenches with a 0.75 μm depth were made in the bitline isolation areas of the planar devices. The trenches were then refilled with thermal and LPCVD (liquid-phase CVD) SiO2. Characterization of the planar EPROM (erasable programmable read-only memory) cell shows that the shallow trench between bitlines has improved their isolation characteristics. An increase in programming efficiency of as much as 30% at a pulse width of 1 ms was observed in the case of the shallow-trench-isolated FAMOS. Additional data indicate the possibility of programming the trench isolated cell at drain voltages lower than the present 12.5 V, thus reducing high voltage requirements
Keywords :
EPROM; insulated gate field effect transistors; semiconductor technology; Si-SiO2; anisotropic etch; bitline isolation areas; buried n+ CVD oxide; buried n+ diffusions; floating-gate avalanche injection; high-density nonvolatile memories; isolation characteristics; n+ SAG FAMOS transistors; oxide-resist etchback process; planar EPROM; planar process; programming efficiency; self-alignment; shallow trench isolation; stacked polysilicon gates; trench etching; Anisotropic magnetoresistance; Chemical vapor deposition; EPROM; Etching; Fabrication; MOSFETs; Nonvolatile memory; PROM; Silicon; Voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.8852
Filename :
8852
Link To Document :
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