DocumentCode
1408899
Title
A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero
Author
Tseng, Wei-Hsin ; Wu, Jieh-Tsorng ; Chu, Yung-Cheng
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
58
Issue
1
fYear
2011
Firstpage
1
Lastpage
5
Abstract
A digital random return-to-zero technique is presented to improve the dynamic performance of current-steering digital-to-analog converters (DACs). To demonstrate the proposed technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90-nm CMOS technology. The DAC achieves a spurious-free dynamic range better than 60 dB for a sine-wave input up to 460 MHz and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.
Keywords
CMOS integrated circuits; digital-analogue conversion; CMOS DAC; current-steering digital-to-analog converters; digital random return-to-zero technique; power 90 mW; size 90 nm; word length 8 bit; CMOS integrated circuits; CMOS technology; Latches; Optical signal processing; Solid state circuits; Switches; Transient analysis; Current steering; digital random return-to-zero (DRRZ); digital-to-analog converter (DAC); return-to-zero (RZ);
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2010.2092823
Filename
5672588
Link To Document