DocumentCode :
1412100
Title :
Multichip Self-Assembly Technology for Advanced Die-to-Wafer 3-D Integration to Precisely Align Known Good Dies in Batch Processing
Author :
Fukushima, Takafumi ; Iwata, Eiji ; Ohara, Yuki ; Murugesan, Mariappan ; Bea, Jichoel ; Lee, Kangwook ; Tanaka, Tetsu ; Koyanagi, Mitsumasa
Author_Institution :
New Ind. Creation Hatchery Center, Tohoku Univ., Sendai, Japan
Volume :
1
Issue :
12
fYear :
2011
Firstpage :
1873
Lastpage :
1884
Abstract :
An advanced die-to-wafer 3-D integration using a surface-tension-driven multichip self-assembly technology was proposed to 3-D stack a large number of known good dies (KGDs) in batch processing. The parallel self-assembly with a unique multichip pick-up tool was newly applied to die-to-wafer 3-D integration to overcome throughput and yield problems in conventional 3-D integration approaches. In addition, novel batch transfer of chips self-assembled on a carrier wafer to the corresponding target wafer was demonstrated. By using the multichip self-assembly, many KGDs can be precisely aligned and temporarily placed on a carrier wafer all at once, and then, the self-assembled KGDs can be simultaneously transferred to another target wafer in a face-to-face bonding manner at the wafer level. Average alignment accuracy was found to be approximately 400 nm when a hundred 3-mm-square chips were self-assembled on carrier wafers with small droplets of an aqueous solution. The alignment accuracy was experimentally proven to be fairly dependent on liquid surface tension as a self-assembly parameter. The liquid wettability contrast between the chip assembly areas and the surrounding areas formed on carrier wafers was another key parameter for alignment accuracy. The former and the latter areas were rendered high hydrophilic and hydrophobic. These areas, respectively, showed water contact angles less than 5° and 115°. Therefore, various sizes of chips (3 × 3 mm, 5 × 5 mm, 4 × 9 mm, and 10 × 10 mm) were self-assembled on a carrier wafer with high alignment accuracy, and further, the self-assembled chips were successfully transferred to the other faced target wafer in a batch.
Keywords :
batch processing (industrial); contact angle; hydrophilicity; hydrophobicity; self-assembly; surface tension; three-dimensional integrated circuits; wafer bonding; wafer level packaging; wetting; 3D stack; KGD; advanced die-to-wafer 3D integration; average alignment accuracy; batch processing; batch transfer; carrier wafers; chip assembly areas; conventional 3D integration; face-to-face bonding manner; faced target wafer; hydrophilicity; hydrophobicity; known good dies; liquid surface tension; liquid wettability contrast; multichip pick-up tool; multichip selfassembly; parallel self-assembly; self-assembled chips; self-assembly parameter; surface-tension-driven multichip self-assembly technology; water contact angles; Accuracy; Assembly; Bonding; Self-assembly; Silicon; Throughput; 3-D integration; alignment and bonding; die-to-wafer stacking; liquid surface tension; self-assembly;
fLanguage :
English
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
2156-3950
Type :
jour
DOI :
10.1109/TCPMT.2011.2160266
Filename :
6119133
Link To Document :
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