DocumentCode
1412901
Title
A Novel Test Flow for One-Time-Programming Applications of NROM Technology
Author
Chao, Mango C -T ; Chin, Ching-Yu ; Tsou, Yao-Te ; Chang, Chi-Min
Author_Institution
Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
19
Issue
12
fYear
2011
Firstpage
2170
Lastpage
2183
Abstract
The NROM technology is an emerging non-volatile-memory technology providing high data density with low fabrication cost. In this paper, we propose a novel test flow for the one-time-programming (OTP) applications using the NROM bit cells. Unlike the conventional test flow, the proposed flow applies the repair analysis in its package test instead of in its wafer test, and hence creates a chance for reusing the bit cells originally identified as a defect to represent the value in the OTP application. Thus, the proposed test flow can reduce the number of bit cells to be repaired and further improve the yield. Also, we propose an efficient and effective estimation scheme to predict the probability of a part being successfully repaired before packaged. This estimation can be used to determine whether a part should be packaged, such that the total profit of the proposed test flow can be optimized. A series of experiments are conducted to demonstrate the effectiveness, efficiency, and feasibility of the proposed test flow.
Keywords
integrated circuit testing; read-only storage; NROM technology; conventional test flow; non-volatile-memory technology; one-time programming; package test; wafer test; Estimation; Mathematical model; Nonvolatile memory; Read only memory; Reliability; NROM; repair rate estimation; test flow;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2010.2087044
Filename
5675765
Link To Document