SP-HV: A Scalable Surface-Potential-Based Compact Model for LDMOS Transistors

Author

Yao, Wei ; Gildenblat, Gennady ; McAndrew, Colin C. ; Cassagnes, Alexandra

Author_Institution

Sch. of Electr., Comput., & Energy Eng., Arizona State Univ., Tempe, AZ, USA

Volume

59

Issue

3

fYear

2012

fDate

3/1/2012 12:00:00 AM

Firstpage

542

Lastpage

550

Abstract

This paper introduces a scalable compact model of lateral double-diffused MOS (LDMOS) transistors. The new model, i.e., the Surface-Potential-based High-Voltage MOS (SP-HV), is constructed from a surface-potential-based bulk MOS field-effect transistor model, i.e., PSP, and a nonlinear resistor model, i.e., R3. Extensions are made to both PSP and R3 for improved modeling of LDMOS devices, and one internal node is introduced to connect the two component models. The new model is validated by comparison to technology computer-aided design (TCAD) simulations and experimental data. Quasi-saturation, self-heating, impact ionization current in the drift region, and complex behavior of transcapacitances are accurately modeled by SP-HV.

Keywords

MOSFET; semiconductor device models; technology CAD (electronics); LDMOS transistor; PSP resistor model; R3 resistor model; SP-HV MOS; TCAD simulation; impact ionization current; lateral double-diffused MOS transistor; nonlinear resistor model; quasisaturation current; scalable surface-potential-based compact model; self-heating current; surface-potential-based bulk MOS field-effect transistor model; surface-potential-based high-voltage MOS; technology computer-aided design simulation; Capacitance; Computational modeling; Impact ionization; Integrated circuit modeling; Logic gates; Resistance; Transistors; Compact model; lateral double-diffused metal–oxide–semiconductor (LDMOS); quasi-saturation; self-heating; surface potential;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2011.2177092

Filename

6121944