Title :
Node sampling technique to speed up probability-based power estimation methods
Author :
Choi, Hoon ; Hwang, Seung Ho
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fDate :
6/25/1998 12:00:00 AM
Abstract :
A new technique, node sampling, is proposed, to speed up probability-based power estimation methods. This technique samples and processes only a small portion of the total nodes to estimate the power consumption of a circuit. It is different from previous speed-up techniques for probability-based methods which reduce the processing time for each node, and is also different from the sampling techniques for simulation-based methods which sample input vector sequences. The experimental results demonstrate the validity of the proposed method
Keywords :
VLSI; circuit CAD; digital integrated circuits; digital simulation; integrated circuit design; probability; VLSI design; input vector sequences; node sampling technique; power consumption; probability-based power estimation; processing time; simulation-based methods; speed-up techniques;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980940
