Title :
Fault Models of CMOS Gates: An Empirical Study Based on Mutation Analysis
Author :
Xiaofeng Tang ; Aiqiang Xu ; Wenhai Li ; Zhiyong Yang
Author_Institution :
Dept. of Sci. Res., Naval Aeronaut. & Astronaut. Univ., Yantai, China
Abstract :
An empirical study is conducted to analyze the fault models of CMOS gates in VLSI. The mutation analysis methodology is used to ensure the simulation experiments are sufficient enough. For the primitive CMOS logic cells: inverter, 2-input NAND, NOR and XOR gates, a total of 335 mutant circuits are generated, simulated and analyzed. Comparing with the previous work, several new fault models are revealed, such as other-logic and the indetermination fault categorys sub-categories: 0-to-X, 1-to-X and other-to-X. Besides, the experimental results show that the classic static stuck-at fault cannot cover many practical defects in a circuit since it just averagely accounts for less than 15% of the total faults. Many other useful conclusions are drawn, which may benefit the related fault-based applications.
Keywords :
CMOS logic circuits; VLSI; fault tolerant computing; logic gates; 0-to-X fault category; 1-to-X fault category; 2-input NAND gates; CMOS gates; NOR gates; VLSI; XOR gates; fault models; inverter; mutant circuits; mutation analysis methodology; other-to-X fault category; primitive CMOS logic cells; static stuck-at fault; Analytical models; CMOS integrated circuits; Circuit faults; Integrated circuit modeling; Logic gates; Semiconductor device modeling; Transistors; CMOS gate; VLSI; fault model; mutation analysis;
Conference_Titel :
Dependable, Autonomic and Secure Computing (DASC), 2014 IEEE 12th International Conference on
Conference_Location :
Dalian
Print_ISBN :
978-1-4799-5078-2
DOI :
10.1109/DASC.2014.29
