Title :
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams
Author :
Chang, Shih-Chieh ; Marek-Sadowdka, M. ; Hwang, TingTing
Author_Institution :
Inst. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
fDate :
10/1/1996 12:00:00 AM
Abstract :
This paper proposes an efficient algorithm for technology mapping targeting table look-up (TLU) blocks. It is capable of minimizing either the number of TLUs used or the depth of the produced circuit. Our approach consists of two steps. First a network of super nodes, is created. Next a Boolean function of each super node with an appropriate don´t care set is decomposed into a network of TLUs. To minimize the circuit´s depth, several rules are applied on the critical portion of the mapped circuit
Keywords :
Boolean functions; circuit optimisation; field programmable gate arrays; logic CAD; table lookup; Boolean function; TLU FPGA; binary decision diagram decomposition; circuit depth; critical portion; don´t care set; mapped circuit; super nodes; table lookup; technology mapping; Boolean functions; Circuits; Computer science; Data structures; Field programmable gate arrays; Logic design; Network synthesis; Programmable logic arrays; Routing; Table lookup;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
