Modeling of resistance in FinFET local interconnect

Author

Ning Lu ; Kotecha, Pooja M. ; Wachnik, Richard A.

Author_Institution

Semicond. R&D Center, IBM, Essex Junction, VT, USA

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

4

Abstract

We present an innovative and comprehensive approach to model the resistance of local interconnect used in finFET technologies. Our parasitic resistance formulas for finFET source/drain regions cover both merged and unmerged fin processes. They have been verified with field solver simulation results, and are found to be accurate over a wide range of parameter values. Our local interconnect resistance model has been used in 14nm finFET technology, and is a critical part of compact models used in both extraction flow and schematic/pre-layout flow.

Keywords

MOSFET; integrated circuit interconnections; integrated circuit layout; semiconductor device models; FinFET local interconnect; compact models; field solver simulation; parasitic resistance formulas; resistance modeling; schematic-pre-layout flow; size 14 nm; source-drain regions; unmerged fin process; Equations; FinFETs; Integrated circuit interconnections; Integrated circuit modeling; Layout; Mathematical model; Resistance; FinFET; local interconnect; parasitic resistance; resistance modeling; schematic model; source/drain resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6946027

Filename

6946027