DocumentCode
142022
Title
Innovative practices session 2C: Advanced in yield learning
Author
Lin, Yen-Tzu ; Benware, Brady ; Stine, Brian ; Bhavnagarwala, Azeez
Author_Institution
Nvidia
fYear
2014
fDate
13-17 April 2014
Firstpage
1
Lastpage
1
Abstract
The onset of FinFET technology nodes brings with it additional challenges in ramping yields due to new defect behaviors and new hardships in the physical failure analysis process. This presentation highlights these challenges and makes the argument that improved scan based diagnosis capabilities that leverage a transistor level understanding of the cells will be necessary to combat these challenges.
Keywords
Abstracts; FinFETs; Graphics; Metrology; Random access memory; Threshold voltage; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2014 IEEE 32nd
Conference_Location
Napa, CA, USA
Type
conf
DOI
10.1109/VTS.2014.6818749
Filename
6818749
Link To Document