Fault tolerant nanoarray circuits: Automatic design and verification

Author

Ranone, P. ; Turvani, Giovanna ; Riente, Fabrizio ; Graziano, Mariagrazia ; Roch, Massimo Ruo ; Zamboni, Maurizio

Author_Institution

Electron. & Telecommun. Dept., Politec. di Torino, Turin, Italy

fYear

2014

fDate

13-17 April 2014

Firstpage

1

Lastpage

6

Abstract

We automatically maximize fault-tolerance in nanoarrays based on silicon nanowires and Gate-All-Around transistors optimizing their topology vs. several distributions of faults inherited by technology. We added a Monte Carlo engine in our nanoarchitecture design tool ToPoliNano and verified the effectiveness of the fault-tolerance algorithm over several circuits and faults distributions.

Keywords

Monte Carlo methods; electronic design automation; fault diagnosis; fault tolerance; integrated circuit design; integrated circuit reliability; integrated circuit testing; logic arrays; nanoelectronics; nanowires; Monte Carlo engine; Si; ToPoliNano; automatic design; automatic verification; fault distribution; fault tolerant nanoarray circuits; gate-all-around transistors; nanoarchitecture design tool; silicon nanowire; Circuit faults; Fault tolerance; Fault tolerant systems; Integrated circuit modeling; Logic gates; Optimization; Transistors; CAD for nanoelectronics; Fault-tolerance optimization; Monte-Carlo; Nanoarrays; emerging technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium (VTS), 2014 IEEE 32nd

Conference_Location

Napa, CA

Type

conf

DOI

10.1109/VTS.2014.6818761

Filename

6818761