Title :
SMV methodology enhancements for high speed I/O links of SoCs
Author :
Viveros-Wacher, Andres ; Alejos, Ricardo ; Alvarez, Luis ; Diaz-Castro, Israel ; Marcial, Brenda ; Motola-Acuna, Gaston ; Vega-Ochoa, Edgar-Andrei
Author_Institution :
Intel Guadalajara Design Center, Intel Corp., Tlaquepaque, Mexico
Abstract :
This paper presents an enhanced methodology to validate High Speed I/O links. The methodology outlines a stress method selection process, statistical techniques to optimize volume data collection as well as a method to determine when to perform UPM calculations.
Keywords :
integrated circuit testing; system-on-chip; SMV methods; SoC; high speed I/O links; statistical techniques; stress method selection process; system marginality validation; system-on-chip; volume data collection; Hidden Markov models; Monte Carlo methods; Sociology; Stress; System-on-chip; Voltage measurement; High Speed I/O; Post-Silicon Electrical Validation; System Marginality Validation; System-on-Chip; Unit per Million;
Conference_Titel :
VLSI Test Symposium (VTS), 2014 IEEE 32nd
Conference_Location :
Napa, CA
DOI :
10.1109/VTS.2014.6818767
