DocumentCode
1427367
Title
Modulo address generators for DSPs
Author
Prasad, M.K. ; Kolagotla, R.K.
Author_Institution
SONY Personal Mobile Commun. of America, San Diego, CA, USA
Volume
34
Issue
17
fYear
1998
fDate
8/20/1998 12:00:00 AM
Firstpage
1653
Lastpage
1654
Abstract
Digital signal processors implement modulo addressing by using separate hardware generation and comparison. To simplify hardware, they restrict the starting address, the displacement value, and/or the buffer length. The authors show that, by rewriting the equations for modulo addressing. It is possible to combine address generation and comparison to simplify hardware without loss in speed
Keywords
adders; buffer storage; digital signal processing chips; shift registers; adder; buffer length; circular buffer; digital signal processors; displacement value; high-speed implementation; modulo address generators; registers; separate hardware generation/comparison; starting address;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19981153
Filename
715272
Link To Document