Title :
Optimised 0.25 μm high performance retrograde well pMOS device for low-power applications
Author :
Toe-Naing, Swe ; Kiat-Seng, Yeo
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
fDate :
8/20/1998 12:00:00 AM
Abstract :
The design optimisation, through device simulation and fabrication, of the 0.25 μm retrograde well surface-channel pMOSFET for low-power applications is presented. The high performance pMOSFET is realised by careful design of both the channel and the LDD doping profile. A high transconductance of 190 mS/mm and an off-current of <1pA/μm is demonstrated
Keywords :
MOS integrated circuits; MOSFET; doping profiles; 0.25 micron; LDD doping profile; channel design; design optimisation; device simulation; fabrication; high performance p-MOSFET; low-power applications; retrograde well pMOS device; surface-channel pMOSFET;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19981178
