Title :
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL
Author :
Kim, Sungjoon ; Lee, Kyeongho ; Moon, Yongsam ; Jeong, Deog-Kyoon ; Choi, Yunho ; Lim, Hyung Kyu
Author_Institution :
Inter-Univ. Semicond. Res. Center, Seoul Nat. Univ., South Korea
fDate :
5/1/1997 12:00:00 AM
Abstract :
This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and r.m.s. jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6 μm CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin
Keywords :
CMOS digital integrated circuits; digital phase locked loops; jitter; signal sampling; system buses; timing circuits; voltage-controlled oscillators; 0.6 micron; 960 Mbit/s; CMOS technology; I/O circuit; VCO; high-speed bus; low jitter PLL; oversampling method; phase-locked loop; skew-tolerant bus interface; Bandwidth; CMOS technology; Circuits; Clocks; Interference; Jitter; Master-slave; Moon; Phase locked loops; Pins;
Journal_Title :
Solid-State Circuits, IEEE Journal of
