• DocumentCode
    1428239
  • Title

    Fan-in restrictions in logic circuits

  • Author

    Zissos, D. ; Duncan, F.G.

  • Author_Institution
    University of Calgary, Department of Mathematics, Statistics & Computing Science, Calgary, Canada
  • Volume
    118
  • Issue
    2
  • fYear
    1971
  • fDate
    2/1/1971 12:00:00 AM
  • Firstpage
    321
  • Lastpage
    327
  • Abstract
    Gate fan-in restrictions in logic circuits can be met at the design level by controlling the size of the sums and products of the corresponding Boolean expressions. A single-step procedure for meeting gate fan-in restrictions by limiting the size of the Boolean sums and products while retaining gate minimality is described. The steps are chosen to allow both hand and computer execution.
  • Keywords
    Boolean functions; logic circuits; logic gates; Boolean functions; formal logic; gate fan in restrictions; logic circuits; logic gates;
  • fLanguage
    English
  • Journal_Title
    Electrical Engineers, Proceedings of the Institution of
  • Publisher
    iet
  • ISSN
    0020-3270
  • Type

    jour

  • DOI
    10.1049/piee.1971.0057
  • Filename
    5250641
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1428239