Title :
A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications
Author :
Jung, Tae-Sung ; Choi, Young-Joon ; Suh, Kong-Deog ; Suh, Byung-Hoon ; Kim, Jin-Ki ; Lim, Young-Ho ; Koh, Yong-Nam ; Park, Jong-Wook ; Lee, Ki-Jong ; Park, Jung-Hoon ; Park, Kee-Tae ; Kim, Jhang-Rae ; Yi, Jeong-Hyong ; Lim, Hyung-Kyu
Author_Institution :
Memory Design Team, Samsung Electron. Co Ltd., Kyungki-Do, South Korea
fDate :
11/1/1996 12:00:00 AM
Abstract :
For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-μm CMOS technology, resulting in a 117 mm2 die size and a 1.1 μm2 effective cell size
Keywords :
CMOS memory circuits; EPROM; NAND circuits; 0.4 micron; 0.5 MB/s; 128 Mbit; 14.0 MB/s; 3.3 V; CMOS technology; NAND flash memory; cell-by-cell operation; inhibit operation; intelligent page buffer; local self-boosting; mass storage; multilevel cell; program disturbance; program operation; program throughput; read throughput; serial access; state-by-state operation; threshold voltage distribution; CMOS technology; Costs; Energy consumption; Flash memory; Magnetic devices; Meteorological radar; Solid state circuits; Threshold voltage; Throughput; Tunneling;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1996.542301
