Title :
A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell
Author :
Ohkawa, Masayoshi ; Sugawara, Hiroshi ; Sudo, Naoaki ; Tsukiji, M. ; Nakagawa, Ken-ichiro ; Kawata, Masato ; Oyama, Ken-ichi ; Takeshima, Toshio ; Ohya, Shuichi
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan
fDate :
11/1/1996 12:00:00 AM
Abstract :
In order to realize high-capacity and low-cost flash memory, we have developed a 64-Mb flash memory with multilevel cell operation scheme. The 64-Mb flash memory has been achieved in a 98 mm2 die size by using four-level per cell operation scheme, NOR type cell array, and 0.4-μm CMOS technology. Using an FN type program/erase cell allows a single 3.3 V supply voltage. In order to establish fast programming operation using Fowler-Nordheim (FN)-NOR type memory cell, we have developed a highly parallel multilevel programming technology. The drain voltage controlled multilevel programming (DCMP) scheme, the parallel multilevel verify (PMV) circuit, and the compact multilevel sense-amplifier (CMS) have been implemented to achieve 128 b parallel programming and 6.3 μs/Byte programming speed
Keywords :
CMOS memory circuits; EPROM; NOR circuits; parallel programming; 0.4 micron; 3.3 V; 64 Mbit; CMOS technology; FN type program/erase cell; Fowler-Nordheim-NOR type memory cell; compact multilevel sense-amplifier; die size; drain voltage controlled multilevel programming; flash memory; multilevel cell; parallel multilevel verify circuit; parallel programming; CMOS technology; Channel hot electron injection; Circuits; Collision mitigation; Flash memory; National electric code; Parallel programming; Threshold voltage; Ultra large scale integration; Voltage control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1996.542302
