Title :
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators
Author :
Mizuno, Hiroyuki ; Matsuzaki, Nozomu ; Osada, K. ; Shinbo, Toshinobu ; Ohki, Nagatoshi ; Ishida, Hiroto ; Ishibashi, Koibashi ; Kure, Tokuo
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
11/1/1996 12:00:00 AM
Abstract :
A 1-V 16-KB (L2) 2-KB (L1) four-way set-associative cache was fabricated using a 0.25-μm CMOS technology for future low-power high-speed microprocessors. Effective latency of 6.9 ns and power consumption of 10 mW at 100 MHz are obtained at a supply voltage of 1 V. This performance is achieved by using a new separated bit-line memory hierarchy architecture (SBMHA) that speeds up latency and reduces power consumption, and domino tag comparators (DTC´s) that reduce the power dissipation of tag comparisons
Keywords :
CMOS memory circuits; cache storage; content-addressable storage; memory architecture; 0.25 micron; 1 V; 10 mW; 100 MHz; 16 KB; 2 KB; 6.9 ns; CMOS technology; domino tag comparators; four-way set-associative cache; low-power high-speed microprocessors; power consumption reduction; separated bit-line memory hierarchy architecture; CMOS technology; Circuits; Delay; Energy consumption; MOSFETs; Memory architecture; Microprocessors; Power dissipation; Technical Activities Guide -TAG; Threshold voltage; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1996.542306
