Title :
Design of asynchronous multilevel sequential circuits
Author :
Duncan, F.G. ; Zissos, D.
Author_Institution :
University of Bristol, Department of Computer Science, University of Bristol, Bristol, UK
fDate :
2/1/1972 12:00:00 AM
Abstract :
A 7-step algorithm for the design of sequential circuits is described. Its use enables engineering constraints such as gate-speed tolerances and fan-in restrictions to be met systematically, and it has been found helpful in meeting system modifications effectively at the design stage. The algorithm is developed with particular reference to NOR circuits; NAND circuits and relay circuits are treated briefly in Appendixes.
Keywords :
asynchronous sequential logic; logic circuits; logic design; sequential circuits; Boolean reduction; NAND circuits; NOR circuits; asynchronous multilevel sequential circuits; design; fan in restrictions; gate minimality; gate speed tolerances; merging; primitive sequential equations; relay circuits; signal substitution;
Journal_Title :
Electrical Engineers, Proceedings of the Institution of
DOI :
10.1049/piee.1972.0024
