SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new tool called SICARELO to automatic synthesis of asynchronous FSMs with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. The proposed tool starts from a popular specification known as Extended Burst Mode (XBM). The tool SICARELO was tested on a set of benchmarks, compared with 3D and Minimalist tools that are state of the art. SICARELO tool obtained a reduction media in the combinatorial logic of 32% of products and 25% of literals in the XBM_AFSM synthesis with local clock.