DocumentCode
143222
Title
Specifications for a multi-standard SBCD/ARGOS-3 integrated UHF satellite receiver
Author
Mendes, C.C.A. ; Cunha, G.C.L. ; Vasilevski, M. ; Bourguet, Vincent ; Catunda, S.Y. ; Lima, R.N. ; Barros, Michelli
Author_Institution
Dept. of Electr. Eng., UFRN, Natal, Brazil
fYear
2014
fDate
25-28 Feb. 2014
Firstpage
1
Lastpage
4
Abstract
The specifications for the front-end design of a SBCD/ARGOS-3 integrated UHF receiver in a 0.13 μm star-dard CMOS process are derived. A low intermediate frequency architecture is presented, in which a 3-stage low-noise amplifier, a passive mixer and a phase-locked loop based frequency synthesizer are employed for achieving the resulting specs.
Keywords
CMOS integrated circuits; frequency synthesizers; low noise amplifiers; mixers (circuits); phase locked loops; receivers; satellite communication; 3-stage low-noise amplifier; low intermediate frequency architecture; multistandard SBCD-ARGOS-3 integrated UHF satellite receiver; passive mixer; phase-locked loop based frequency synthesizer; standard CMOS process; Gain; Mixers; Noise measurement; Phase noise; Receivers; Satellites; ARGOS-3; CMOS; SBCD; UHF Receiver;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (LASCAS), 2014 IEEE 5th Latin American Symposium on
Conference_Location
Santiago
Print_ISBN
978-1-4799-2506-3
Type
conf
DOI
10.1109/LASCAS.2014.6820286
Filename
6820286
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