A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation

Author

Seon-Kyoo Lee ; Byungsub Kim ; Hong-June Park ; Jae-Yoon Sim

Author_Institution

Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol. (POSTECH), Pohang, South Korea

Volume

48

Issue

9

fYear

2013

fDate

Sept. 2013

Firstpage

2118

Lastpage

2127

Abstract

This paper presents an adaptive far-end crosstalk cancellation scheme for a single-ended parallel receiver. The adaptation engine is embedded in a single representative channel CDR, and the receiver efficiently reduces the crosstalk noise with a minimal cost in hardware and power consumption. In addition, the proposed scheme can be applied to any given CDR and equalizing circuits. The receiver is fabricated in 0.13 μm CMOS technology and achieves a reduction of FEXT-induced jitter up to 75%. The receiver consumes 65 mW at 5 Gb/s (4.3 mW/Gb/s/pin) including a PLL for global clock distribution.

Keywords

CMOS integrated circuits; clock and data recovery circuits; clocks; crosstalk; equalisers; phase locked loops; CMOS technology; FEXT-induced jitter reduction; PLL; adaptation engine; adaptive crosstalk-induced jitter cancellation; adaptive far-end crosstalk cancellation scheme; bit rate 5 Gbit/s; crosstalk noise reduction; equalizing circuit; global clock distribution; power 65 mW; single representative channel CDR; single-ended parallel receiver; size 0.13 mum; Capacitance; Couplings; Crosstalk; Jitter; Microstrip; Noise; Receivers; Adaptive crosstalk cancellation; CDRs; crosstalk- induced jitter; far-end crosstalk; parallel links; single-ended signaling;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2013.2264618

Filename

6548094